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hy5du28422b(l)t hy5du28822b(l)t this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.3/may. 02 1 128m-s ddr sdram hy5du28422b(l)t hy5du28822b(l)t
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 2 revision history 1. revision 0.1 (mar. 02) 1) define preliminary sepcification 2. revision 0.2 (apr. 02) 1) change idd4r/4w spec. 3. revision 0.3 (may. 02) 1) input leakage current chan ged from +/-5ua to +/-2ua
description the hynix hy5du28422b(l)t and hy5d u28822b(l)t are a 134,217,728-bit cmos double data rate(ddr) synchro- nous dram, ideally suited for the main memory applications which requires large memory density and high band- width. the hynix 128mb ddr sdrams offer fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on th e rising edges of the ck (falling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ?v dd , v ddq = 2.5v +/- 0.2v ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock in puts (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs) ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? on chip dll align dq and dqs transition with ck transition ? dm mask write data-in at the both rising and falling edges of the data strobe ? tras lock-out function supported ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable /cas latency 2 and 2.5 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal four bank operations with single pulsed /ras ? auto refresh and self refresh supported ? 4096 refresh cycles / 64ms ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? full and half strength driver option controlled by emrs ordering information * x means speed grade part no. configuration package hy5du28422b(l)t-x* 32mx4 400mil 66pin tsop-ii hy5du28822b(l)t-x* 16mx8 preliminary rev. 0.3/may. 02 3 operating frequency grade cl2 cl2.5 remark (cl-trcd-trp) - j 133mhz 166mhz ddr333 (2.5-3-3) -m 133mhz 133mhz ddr266 (2-2-2) - k 133mhz 133mhz ddr266a (2-3-3) - h 100mhz 133mhz ddr266b (2.5-3-3) - l 100mhz 125mhz ddr200 (2-2-2) hy5du28422b(l)t hy5du28822b(l)t
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 4 pin configuration(tsop) row and column address table items 32mx4 16mx8 organization 8m x 4 x 4banks 4m x 8 x 4banks row address a0 - a11 a0 - a11 column address a0-a9, a11 a0-a9 bank address ba0, ba1 ba0, ba1 auto precharge flag a10 a10 refresh 4k 4k 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss 400mil x 875mil 66pin tsop -ii 0.65mm pin pitch x 8 x 4 x 4 x 8
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 5 pin description pin type description ck, /ck input clock: ck and /ck are differen tial clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activa tes, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all ba nks idle), or active power down (row active in any bank). cke is synchronous fo r power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during powe r down. input buffers, excluding cke are disabled during self refresh. cke is an ss tl_2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select : enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a11 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, /we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. dm (ldm, udm) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high al ong with that input data during a write access. dm is sampled on both edges of dqs. although dm pins ar e input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-q7; udm corre- sponds to the data on dq8-q15. dqs (ldqs, udqs) i/o data strobe: output with read data, input with write data. edge aligned with read data, centered in write data. used to capture writ e data. for the x16, ldqs corresponds to the data on dq0-q7; udqs correspo nds to the data on dq8-q15. dq i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 6 command decoder clk /clk cke /cs /ras /cas /we dm address buffer add bank control 8mx4/bank0 column decoder column address counter sense amp 2-bit prefetch unit 8mx4/bank1 8mx4/bank2 8mx4/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2-bit prefetch unit ds dq [0:3] 84 4 8 clk_dll ba0, ba1 functional block diagram (32mx4) 4banks x 8mbit x 4 i/o double data rate synchronous dram
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 7 command decoder clk /clk cke /cs /ras /cas /we dm address buffer add bank control 4mx8/bank0 column decoder column address counter sense amp 2-bit prefetch unit 4mx8/bank1 4mx8/bank2 4mx8/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2-bit prefetch unit ds dq [0:7] 16 8 8 16 clk_dll ba0,ba1 functional block diagram (16mx8) 4banks x 4mbit x 8 i/o double data rate synchronous dram
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 8 simplified command truth table command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register seth x llll op code 1,2 mode register set h x llll op code 1,2 device deselect hx hxxx x1 no operation lhhh bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h lllh x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode entry h l hxxx x 1 lvvv 1 exit l h x 1 note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a11 and ba0~ba1 us ed for mode register setting duing extended mrs or mrs. before entering mode re gister set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last data-i n to prechage delay(tdpl) which is also called write recovery tim e (twr) is needed to guarantee that the last data has been completely written. 5. if a10/ap is high when precharge command being issued, ba0/ba1 are ignored and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x=don?t care, v=va lid data input, op code=operand code, nop=no operation )
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 9 write mask truth table function cken-1 cken /cs, /ras, /cas, /we dm addr a10/ap ba note data write h x x l x 1 data-in mask h x x h x 1 note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. in case of x16 data i/o, ldm and udm control lower byte(dq0~7) and upper byte(dq8~15) respectively.
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 10 operation command truth table-i current state /cs /ras /cas /we address command action idle hxxx x dsel nop or power down 3 lhhh x nop nop or power down 3 lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation llhl ba, ap pre/pall nop lllh x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active hxxx x dsel nop lhhh x nop nop lhhl x bst illegal 4 l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 llhhba, ra act illegal 4 llhl ba, ap pre/pall precharge 7 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst terminate burst l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal 4 l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 11 operation command truth table-ii current state /cs /ras /cas /we address command action write llhhba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge lllh x aref/sref illegal 11 llllopcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end lhhl x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 pre- charge hxxx x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp lllh x aref/sref illegal 11 llllopcode mrs illegal 11
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 12 operation command truth table-iii current state /cs /ras /cas /we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,9,10 llhl ba, ap pre/pall illegal 4,10 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 write recovering with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl lhhl x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 llhhba, ra act illegal 4,10 llhl ba, ap pre/pall illegal 4,11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 refreshing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 13 operation command truth table-iv note : 1. h - logic high level, l - logic low leve l, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge address, ca - column address, ra - row address, nop - no operation. 2. all entries assume that cke was active(high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be legal in the bank indicated by bank addr ess(ba) depending on the state o f that bank. 5. if both banks are idle and cke is inactive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. current state /cs /ras /cas /we address command action write l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd lhhl x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 llhhba, ra act illegal 11 llhl ba, ap pre/pall illegal 11 lllh x aref/sref illegal 11 llllopcode mrs illegal 11
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 14 cke function truth table note : when cke=l, all dq and dqs must be in hi-z state. 1. cke and /cs must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. all command can be stored after 2 clocks from low to high transition of cke. 3. illegal if clk is suspended or stopped during the power down mode. 4. self refresh can be entered on ly from the all banks idle state. 5. disabling clk may cause malfunction of any bank which is in active state. current state cken- 1 cken /cs /ras /cas /we /add action self refresh 1 h xxxxxx invalid l h h x x x x exit self refresh, enter idle after tsrex l h l h h h x exit self refresh, enter idle after tsrex l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l lxxxxx nop, continue self refresh power down 2 h xxxxxx invalid l h h x x x x exit power down, enter idle l h l h h h x exit power down, enter idle l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop, continue power down mode all banks idle 4 h h x x x x x see operation command truth table hllllhx enter self refresh h l h x x x x exit power down h l l h h h x exit power down h l l h h l x illegal h l l h l x x illegal h l l l h x x illegal hlllllx illegal l lxxxxx nop any state other than above h h x x x x x see operation command truth table h lxxxxx illegal 5 l hxxxxx invalid l lxxxxx invalid
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 15 simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre- charge power-up power applied mode register set power down write with autopre- charge power down write read with autopre- charge bank active read self refresh
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 16 power-up sequence and device initialization ddr sdrams must be powered up and initialized in a pred efined manner. operational procedures other than those specified may result in undefined operation. power must fi rst be applied to vdd, then to vddq, and finally to vref (and to the system vtt). vtt must be applied after vddq to avoid device latch-up, which may cause permanent dam- age to the device. vref can be applied anytime after vddq , but is expected to be nominally coincident with vtt. except for cke, inputs are not recognized as valid until after vref is applied. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. maintaining an lvcmos low level on cke during power-up is required to guarantee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal oper- ation (by a read access). after all power supply and refere nce voltages are stable, and the clock is stable, the ddr sdram requires a 200us delay prior to applying an executable command. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharg e all command should be applied. next a extended mode register set command should be issued for the ex tended mode register, to en able the dll, then a mode register set command should be issued for the mode register, to reset th e dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any command. during the 200 cycles of ck, for dll locking, executable commands are disallowed (a de select or nop command must be applied). after the 200 clock cycles, a precharge all command should be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i .e. to program operating para meters without resetting the dll) must be performed. following these cycles , the ddr sdram is ready for normal operation. 1. apply power - vdd, vddq, vtt, vref in the following po wer up sequencing and attemp t to maintain cke at lvc- mos low state. (all the other input pins may be undefined.) ? vdd and vddq are driven from a single power converter output. ? vtt is limited to 1.44v (ref lecting vddq(max)/2 + 50mv vref variation + 40mv vtt variation. ? vref tracks vddq/2. ? a minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the vtt supply into any pin. ? if the above criteria cannot be met by the system desi gn, then the following sequen cing and voltage relation- ship must be adhered to during power up. 2. start clock and maintain stable clock for a minimum of 200usec. 3. after stable power and clock, apply nop condition and take cke high. 4. issue extended mode register set (emrs) to enable dll. 5. issue mode register set (mrs) to reset dll and set devi ce to idle state with bit a8=high. (an additional 200 cycles of clock are required for locking dll) 6. issue precharge commands for all banks of the device. voltage description sequencing voltage relationship to avoid latch-up vddq after or with vdd < vdd + 0.3v vtt after or with vddq < vddq + 0.3v vref after or with vddq < vddq + 0.3v
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 17 7. issue 2 or more auto refresh commands. 8. issue a mode register set command to initia lize the mode register with bit a8 = low. power-up sequence /clk clk vdd dqs dq?s mrs aref pre nop mrs emrs pre nop code code code code code code code code code vddq vref cke cmd ba0,ba1 a10 addr dm ? ???? ? ? ?? ? ? ? ?? ? ? ?? ? ? ?? ? ? tvtd t=200usec tmrd 200 cycles of ck* trp trfc power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) *200 cycles of ck are required (for dll locking) before any executable command can be applied. vtt trp tis tih
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 18 mode register set (mrs) the mode register is used to store the various operating mo des such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is pr ogramed via mrs command. this command is issued by the low signals of /ras, /cas, /cs, /we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode regi ster set command can be issued. two cycles are required to write the data in mode register. during the mrs cycle, an y command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 rfu dr tm cas latency bt burst length a2 a1 a0 burst length sequential interleave 0 0 0 reserved reserved 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 000 reserved 001 reserved 010 2 011 reserved 100 reserved 101 reserved 110 2.5 111 reserved a7 te s t mo de 0normal 1 vendor te s t mo de a8 dll reset 0no 1yes ba0 mrs type 0mrs 1emrs
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 19 burst definition burst length & type read and write accesses to the ddr sdram are burst orient ed, with the burst length be ing programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. burst lengths of 2, 4, or 8 locations are availabl e for both the sequential an d the interleaved burst types. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the bu rst length is set to two, by a 2 -ai when the burst length is set to four and by a 3 -ai when the bu rst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (l east significant) address bit(s) is (are ) used to select the starting location within the block. the programmed burst leng th applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column addres s, as shown in burst definitionon table burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 20 cas latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2 or 2.5 clocks. if a read command is registered at clock edge n, and the la tency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. dll reset the dll must be enabled for normal operation. dll enable is required during power up in itialization, and upon return- ing to normal operation after having di sabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to al low time for the internal cloc k to lock to the externally applied clock before an any command can be issued. output driver impedance control the normal drive strength for all outputs is specified to be sstl_2, class ii. hynix also supports a half strength driver option, intended for lighter load and/or point-to-point environments . selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. i-v curves for both the full strength driver and the half strength driver are included in this document.
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 21 extended mode register set (emrs) the extended mode register controls fu nctions beyond those contro lled by the mode register; these additional func- tions include dll enable/disable, output driver strength sele ction(optional). these function s are controlled via the bits shown below. the extended mode register is programmed via the mode register set command ( ba0=1 and ba1=0) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subseque nt operation. violating either of these requirements will result in unspecified operation. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 01 rfu* 0**dsdll a0 dll enable 0enable 1diable ba0 mrs type 0mrs 1emrs a1 output driver impedance control 0 full strength driver 1 half strength driver * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage ** this part do not support /qfc function, a2 must be programmed to zero.
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 22 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on vref may not exceed +/- 2% of the dc value. dc characteristics i (ta=0 to 70 c , voltage referenced to v ss = 0v) note : 1. vin = 0 to 3.6v, all other pins are not tested und er vin =0v. 2. dout is disabled, vout=0 to 2.7v parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 o c ? sec parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*vddq 0.5*vddq 0.51*vddq v 3 parameter symbol min. max unit note input leakage current i li -2 2 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol -v tt - 0.76 v i ol = +15.2ma
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 23 dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) 32mx4 / 16mx8 parameter symbol test condition speed unit note -j -m -k -h -l operating current idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 90 80 80 80 80 ma operating current i dd1 one bank; active - read - precharge; burst=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 110 100 100 100 80 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 20 15 15 15 15 ma idle standby current i dd2f /cs=high, all banks idle; tck=tck(min); cke=high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 40 35 35 35 30 ma active power down standby current i dd3p one bank active; power down mode ; cke=low, tck=tck(min) 20 20 20 20 20 ma active standby current i dd3n /cs=high; cke=high; one bank; active- precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 40 40 40 40 40 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and cont rol inputs changing once per clock cycle; tck=tck(min); iout=0ma 230 190 190 190 150 ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 230 190 190 190 150 ma auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 160 150 150 150 140 ma self refresh current i dd6 cke=<0.2v; external clock on; tck=tck(min) normal 22222ma low power 11111ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition 300 260 260 260 220 ma
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 24 detailed test conditions for ddr sdram idd1 & idd7 idd1 : operating curren t: one bank operation 1. only one bank is accessed with trc(min), burs t mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 2. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=2, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2 .5, bl=2, trcd = 3*tck, trc = 9*tck, tras = 6*tck read : a0 n n r0 n p0 n n n a0 n - re peat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl =2, bl=2, trcd = 3*tck, trc = 9*tck, tras = 6*tck read : a0 n n r0 n p0 n n n a0 n - re peat the same timing with random address changing 50% of data changing at every burst - ddr266(133mhz, cl=2) : tck = 7.5ns, cl =2, bl=2, trcd = 2*tck, trc = 8*tck, tras = 6*tck read : a0 n r0 n n n p0 n a0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr333(166mhz, cl=2.5) : tck = 6ns, cl=2 , bl=2, trcd = 3*tck, trc = 10*tck, tras = 7*tck read : a0 n n r0 n n n p0 n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop idd7 : operating current: four bank operation 1. four banks are being interleaved wi th trc(min), burst mode, address and control inputs on nop edge are not changing. lout = 0ma 2. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trrd = 2*tck, trcd = 3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl =4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3*tck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr333(166mhz, cl=2.5) : tck = 6ns, cl=2.5, bl=4 , trrd = 2*tck, trcd = 3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 25 ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference betw een the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltag e, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltag e, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )50 ? series resistor (r s )25 ? output load capacitance for access time measurement (c l )30 pf
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 26 ac characteristics i (ac operating conditions unless otherwise noted) parameter symbol ddr333 ddr266(2-2-2) unit note min max min max row cycle time t rc 60 - 60 - ns auto refresh row cycle time t rfc 72 - 75 - ns row active time t ras 42 70k 45 120k ns active to read with auto precharge delay t rap 18 - 15 - ns 16 row address to column address delay t rcd 18 - 15 - ns row active to row active delay t rrd 12 - 15 - ns column address to column address delay t ccd 1-1-ck row precharge time t rp 18 - 15 - ns write recovery time twr 15 - 15 - ns write to read command delay t wtr 1-1-ck auto precharge write recovery + precharge time t dal (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) -ck15 system clock cycle time cl = 2.5 t ck 6127.512ns cl = 2 7.5 12 7.5 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.7 0.7 -0.75 0.75 ns dqs-out edge to clock edge skew t dqsck -0.6 0.6 -0.75 0.75 ns dqs-out edge to data-out edge skew t dqsq -0.45- 0.5ns data-out hold time from dqs t qh t hp -t qhs - t hp -t qhs -ns1, 10 clock half period t hp min (tcl,tch) - min (tcl,tch) -ns1,9 data hold skew factor t qhs - 0.55 - 0.75 ns 10 valid data output window t dv t qh -t dqsq t qh -t dqsq ns data-out high-impedance window from ck, /ck t hz -0.7 0.7 -0.75 0.75 ns 17 data-out low-impedance window from ck , /ck t lz -0.7 0.7 -0.75 0.75 ns 17 input setup time (fast slew rate) t is 0.75 - 0.9 - ns 2,3,5,6 input hold time (fast slew rate) t ih 0.75 - 0.9 - ns 2,3,5,6 input setup time (slow slew rate) t is 0.8 - 1.0 - ns 2,4,5,6
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 27 input hold time (slow slew rate) t ih 0.8 - 1.0 - ns 2,4,5,6 input pulse width t ipw 2.2 2.2 ns 6 write dqs high level width t dqsh 0.35 - 0.35 - ck write dqs low level width t dqsl 0.35 - 0.35 - ck clock to first rising edge of dqs-in t dqss 0.75 1.25 0.72 1.28 ck data-in setup time to dqs-in (dq & dm) t ds 0.45 - 0.5 - ns 6,7, 11~13 data-in hold time to dqs-in (dq & dm) t dh 0.45 - 0.5 - ns 6,7, 11~13 dq & dm input pulse width t dipw 1.75 - 1.75 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0-0-ck write dqs preamble hold time t wpreh 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2-2-ck exit self refresh to any execute command t xsc 200 - 200 - ck 8 average periodic refresh interval t refi - 15.6 - 15.6 us parameter symbol ddr333 ddr266(2-2-2) unit note min max min max
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 28 ac characteristics ii (ac operating conditions unless otherwise noted) parameter symbol ddr266a ddr266b ddr200 unit note min max min max min max row cycle time t rc 65 - 65 - 70 - ns auto refresh row cycle time t rfc 75 - 75 - 80 - ns row active time t ras 45 120k 45 120k 50 120k ns active to read with auto precharge delay t rap 20 - 20 - 20 - ns 16 row address to column address delay t rcd 20 - 20 - 20 - ns row active to row active delay t rrd 15 - 15 - 15 - ns column address to column address delay t ccd 1-1-1-ck row precharge time t rp 20 - 20 - 20 - ns write recovery time twr 15 - 15 - 15 - ns write to read command delay t wtr 1-1-1-ck auto precharge write recovery + precharge time t dal (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) -ck15 system clock cycle time cl = 2.5 t ck 7.5127.5128.012ns cl = 2 7.5 12 10 12 10 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to clock edge skew t dqsck -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to data-out edge skew t dqsq - 0.5 - 0.5 - 0.6 ns data-out hold time from dqs t qh t hp -t qhs - t hp -t qhs - t hp -t qhs -ns1, 10 clock half period t hp min (tcl,tch) - min (tcl,tch) - min (tcl,tch) -ns1,9 data hold skew factor t qhs - 0.75 - 0.75 - 0.75 ns 10 valid data output window t dv t qh -t dqsq t qh -t dqsq t qh -t dqsq ns data-out high-impedance window from ck, /ck t hz -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17 data-out low-impedance window from ck , /ck t lz -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 29 -continued- parameter symbol ddr266a ddr266b ddr200 unit note min max min max min max input setup time (fast slew rate) t is 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input hold time (fast slew rate) t ih 0.9 - 0.9 - 1.1 - ns 2,3,5,6 input setup time (slow slew rate) t is 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input hold time (slow slew rate) t ih 1.0 - 1.0 - 1.1 - ns 2,4,5,6 input pulse width t ipw 2.2 2.2 2.5 - ns 6 write dqs high level width t dqsh 0.35 - 0.35 - 0.35 - ck write dqs low level width t dqsl 0.35 - 0.35 - 0.35 - ck clock to first rising edge of dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 ck data-in setup time to dqs-in (dq & dm) t ds 0.5 - 0.5 - 0.6 - ns 6,7, 11~13 data-in hold time to dqs-in (dq & dm) t dh 0.5 - 0.5 - 0.6 - ns dq & dm input pulse width t dipw 1.75 - 1.75 - 2 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0-0-0-ck write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2-2-2-ck exit self refresh to any execute command t xsc 200 - 200 - 200 - ck 8 average periodic refresh interval t refi - 15.6-15.6-15.6us
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 30 n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a11, ba0~ba1, cke, / cs, / ras, / cas, / we. 3. for command/address input slew rate>=1.0v/ns 4. for command/address input slew rate>=0.5v/ns and <1.0v/ns this derating table is used to increase tis/tih in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 5. ck, /ck slew rates are>=1.0v/ns 6. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. data latched at both rising and falling ed ges of data strobes(ldqs/udqs) : dq, ldm/udm. 8. minimum of 200 cycles of stable input clocks after self refres h exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. 9. min (tcl, tch) refers to the smaller of the actual clock low ti me and the actual cloc k high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). 10. thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on-chip clock circuits, da ta pin to pin skew and output pattern effects and p-channel t o n-channel variation of the output drivers. 11. this derating table is used to increase tds/tdh in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 12. i/o setup/hold plateau derating. this derating table is used to increase tds/tdh in case where the input level is flat below vref +/-310mv for a duration of up to 2ns. 13. i/o setup/hold delta inverse slew rate derating. this derating table is used to increase tds/tdh in case where the dq and dqs slew rates differ. the delta inverse slew rate is calculated as (1/slewrate1)-(1/s lewrate2). for example, if slew rate 1= 0.5v/ns and slew rate2=0.4v/n then th e delta inverse slew rate=-0.5ns/v. input setup / hold slew-rate delta tis delta tih v/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0 input setup / hold slew-rate delta tds delta tdh v/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level delta tds delta tdh mv ps ps +280 +50 +50 (1/slewrate1)-(1/slewrate2) delta tds delta tdh ns/v ps ps 000 +/-0.25 +50 +50 +/- 0.5 +100 +100
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 31 14. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through th e dc region must be monotonic. 15. tdal = (tdpl / tck ) + (trp / tck ). for each of the terms above, if not already an integer, round to the next highest int eger. tck is equal to the actual system clock cycle time. example: for ddr266b at cl=2.5 and tck = 7.5 ns, tdal = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) round up each non-integer to the next highest integer: = (2) + (3), tdal = 5 clocks 16. for the parts which do not has internal ras lockout circuit, active to read with auto precharge delay should be tras - (bl/2) x tck. 17. thz and tlz transitions occur in the same access time window s as valid data trasitions. these parameters are not reference d to a specific voltage level but specify when the device output is no longer driving (hz), or begins driving (lz).
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 32 v ref v tt r t =50 ? zo=50 ? c l =30pf output capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 2.3v to 2.7v, v o dc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by desi gn and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, /ck c i1 2.0 3.0 pf delta input clock capacitance ck, /ck delta c i1 -0.25pf input capacitance all other input-only pins c i1 2.0 3.0 pf delta input capacitance all other input-only pins delta c i2 -0.5pf input / output capacitance dq, dqs, dm c io 4.0 5.0 pf delta input / output capacitance dq, dqs, dm delta c io -0.5pf
hy5du28422b(l)t hy5du28822b(l)t rev. 0.3/may. 02 33 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch) package information 400mil 66pin thin sm all outline package note : package do not mold protrusion. allowable protrusion of both sides is 0.4mm.

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